1. Field of the Invention
The present invention relates to a wiring substrate on which a semiconductor chip is mounted, a semiconductor device using the wiring substrate, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Recent semiconductor devices with improved performance, increased number of functions, and increased density have an accordingly increased number of terminals arranged at a reduced pitch. Thus, wiring substrates for packaging on which semiconductor devices are mounted have been desired to have more densely arranged interconnections of further reduced sizes.
Built-up printed substrates, a kind of multilayer wiring substrate, have been commonly used as wiring substrates for packaging. In the built-up printed substrate, resin layers are formed on a top surface and a bottom surface of a glass epoxy printed substrate which serves as a base core substrate and on which interconnections are formed. Via holes are formed in the resin layers by the photolithographic process and the laser process. Interconnection layers and via conductors are then formed by plating and photolithography. A multilayer interconnection structure can be formed by repeating the resin layer forming step and the interconnection and via conductor forming step as required.
However, a problem with the built-up printed substrate is that because of the use of a glass epoxy printed substrate of low heat resistance as the base core substrate, deformation such as warpage or waviness is apt to occur in the substrate by heating during the formation of a multilayer structure or the mounting of a semiconductor chip.
On the other hand, the JP2000-3980A (Patent Document 1) discloses an wiring substrate for packaging in which a built-up laminated structure is formed on a base substrate made of a metal sheet.
FIG. 12 shows a diagram of a process of manufacturing the wiring substrate for packaging. First, as shown in FIG. 12(a), an insulating layer 502 is formed on a metal sheet 501. A via hole. 503 is formed in the insulating layer 502. Then, as shown in FIG. 12(b), an interconnection pattern 504 is formed on the insulating layer 502 with the via hole 503 formed therein. Then, as shown in FIG. 12(c), an insulating layer 506 is formed on the interconnection pattern 504. A flip chip pad portion 505 extending to the interconnection pattern 504 is formed in the insulating layer 506. Finally, as shown in FIG. 12(d), the metal sheet 501 is etched from its bottom surface to form a substrate-reinforcing body 507 and external electrode terminals 508.
However, since in this wiring substrate for packaging, the external electrode terminals 508 are formed by etching the metal sheet 501, it is difficult to reduce the pitch between the external electrode terminals 508 owing to limits to the control of the amount of side etching. When the wiring substrate for packaging is mounted on an external board or in a device, stress concentrates at the interface between the external electrode terminal 508 and the insulating layer 502 because of the structure of the substrate. This disadvantageously increases the likelihood of open faults and prevents the substrate from being sufficiently reliable.
A wiring substrate for packaging capable of solving the above problems with the conventional techniques is disclosed in JP2002-198462A (Patent Document 2).
With reference to FIG. 13, description will be given of the basic structure of this wiring substrate and a method of forming the wiring substrate. First, an electrode 602 is formed on a support board 601 made of a metal sheet or the like. An insulating layer 603 is formed so as to cover the electrode 602. Then, a via hole 604 extending to the electrode 602 is formed in the insulating layer 603. An interconnection 605 is formed so as to fill the via hole 604. The interconnection 605 is connected to the electrode 602 by a conductor buried in the vial hole 604 (FIG. 13(a)). A multilayer interconnection structure can be formed by repeating the steps of forming an insulating layer, forming a via hole, and forming an interconnection as required. Then, as shown in FIG. 13(b), the support board 601 is selectively partly etched away to expose the electrode 602 and to form a support body 606. A wiring substrate 607 can thus be formed. The formation of a pad-like electrode pattern has been described here. However, a linear interconnection pattern can be similarly formed.
The support body 606 made of a heat-resistant material such as metal enables thermal deformation of the wiring substrate to be inhibited. The insulating layer made of a resin material of a desired mechanical strength provides a wiring substrate having a higher strength. Moreover, the bottom surfaces of conductor layers that constitute electrodes or interconnections are exposed with the peripheries of the conductor layers buried in the insulating layer. This inhibits stress concentration on the conductor layers during mounting, and improves mounting reliability.
Insulating layer materials suitable for the above wiring substrate are disclosed in JP2004-179647 A (Patent Document 3). To provide a wiring substrate and a semiconductor package which can inhibit generation of cracks caused by repeatedly applied thermal stress, offering improved reliability, this publication discloses an insulating layer in which when it has a film thickness of 3 to 100 μm and a fracture strength of at least 80 MPa at 23° C. and when the fracture strength at −65° C. is defined as a and the fracture strength at 150° C. is defined as b, the value of ratio (a/b) is at most 4.5. The publication also specifies that the insulating layer preferably exhibits a modulus of elasticity of at least 2.3 GPa at 150° C. The publication also discloses that when the modulus of elasticity at −65° C. is defined as c and the modulus of elasticity at 150° C. is defined as d, the value of the ratio (c/d) is specified to be at most 4.7. The publication further discloses that the value of the ratio (a/b) is at most 2.5 or greater than 2.5 and at most 4.5 and that the difference between the ratio (a/b) and the ratio (c/d) is specified to be at most 0.8.
On the other hand, proposal has been made of a technique for forming a dummy pattern in a part (sacrificing board part) of a wiring substrate other than its product part wherein semiconductor chips are mounted, in order to enhance the rigidity of the wiring substrate and to reduce warpage and waviness (distortion).
For example, JP8-51258 A (Patent Document 4) describes that a dummy pattern including hexagonal patterns arranged like a honeycomb is formed in a sacrificing board part of a wiring substrate to allow its rigidity to be enhanced. The publication also describes that the ratio of the area of the dummy pattern in the sacrificing board part to the area of the part with no dummy pattern is set almost equal to the ratio of the area of the interconnection pattern in the product part to the area of the part with no interconnection pattern to reduce warpage and distortion.
Further, JP11-177191 A (Patent Document 5) describes a wiring substrate having a solid pattern formed in a sacrificing board part located on a side thereof perpendicular to a transfer direction for component mounting and a dummy pattern formed in a sacrificing board part located on a side thereof parallel to the transfer direction for component mounting, the dummy pattern being composed of a plurality of divided pattern units. The publication describes rectangular or circular pattern units arranged at regular intervals as the dummy pattern in the sacrificing board part. According to the publication, the solid pattern enhances rigidity and the divided dummy pattern reduces warpage and distortion. Further, the rigidity of the substrate of a multilayer structure can be enhanced by varying the shape or arrangement pitch of the pattern units for each layer.
In contrast to the technique for reducing warpage and waviness on the basis of the structure (pattern structure) of a substrate itself, a technique has been proposed which improves mounting capability on the basis of a device in which a semiconductor chip is mounted and a method of mounting. For example, JP2001-68510 A (Patent Document 6) describes a method of mounting a semiconductor chip on a warped substrate using a bonding device that mounts a semiconductor chip on the basis of a flip chip scheme. According to the publication, a substrate is placed on a stage with a suction hole. A pressure reducing mechanism is then used to generate a suction force in the suction hole to allow the bottom surface of the substrate to be sucked and held by a surface of the stage. At this time, the warpage of the substrate is corrected to make the substrate parallel to the stage surface. A substrate holding mechanism pushes the substrate against the stage. This brings the substrate into accurate, tight contact with the stage, eliminating the gap between the substrate and the stage to prevent air leakage. This enables the prevention of a possible decrease in holding force resulting from air leakage, allowing the prevention of possible misalignment between the substrate and semiconductor chip during a stage operation or bonding.
The present inventors have recognized as follows. A growing need for thinner substrates prevents the conventional warpage inhibiting techniques from exerting a sufficient warpage inhibiting effect particularly on substrates having interconnection structures such as the one described in Patent Document 2. If a wiring substrate with no semiconductor chip mounted yet is warped on a stage, the wiring substrate may be misaligned with respect to the stage when placed on and fixed to the stage, or transferring the wiring substrate may become difficult. This unfortunately degrades the reliability and productivity of products.
Even if a wiring substrate is placed on a stage using a method such as the one described in Patent Document 6, the substrate with a semiconductor chip mounted thereon may disadvantageously be warped with its central part raised along the transfer direction. When the substrate is warped with its central part raised, during transfer thereof, the substrate with the chip mounted thereon may disadvantageously comes into contact with a member that is located over a transfer route such as a substrate holding guide or a heating cover.